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Meta ASIC Engineer, Design Verification in Austin, Texas

Summary:

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Required Skills:

ASIC Engineer, Design Verification Responsibilities:

  1. Develop functional tests based on verification test plan.

  2. Duties include: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.

  3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

  4. Debug root-cause and resolve functional failures in the design, partnering with the Design Team.

  5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon Validation Teams towards ensuring design quality.

  6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications:

Minimum Qualifications:

  1. Requires a Master’s degree in Computer Science, Engineering, Electrical Engineering, or a related field and 60 months of experience in the job offered or in a computer-related occupation. Foreign equivalent accepted. Must have 60 months of experience in each of the following:

    1. Architecting and implementing Design Verification infrastructure and executing the full verification cycle

    1. Verification in Emulation platform using C++/Perspec System Verifier
    1. Creating tests and debugging test issues on emulation platform
    1. “First-pass success” in ASIC development cycles
    1. Verilog, SystemVerilog, C/C++ based verification and UVM methodology
    1. IP/sub-system or SoC level verification based on SystemVerilog UVM/OVM based methodologies
    1. Functional verification, including SV Assertions, Formal or Emulation
    1. EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Public Compensation:

$188,062/year to $234,520/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

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