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Meta Design Verification Engineer in Sunnyvale, California

Summary:

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Required Skills:

Design Verification Engineer Responsibilities:

  1. Develop and perform operational, maintenance, and testing procedures for System on Chip based electronic product components.

  2. Work with researchers and architects defining verification methodologies for each of the different core Intellectual Property (IP).

  3. Define and track detailed test plans for the different electronic modules and top levels.

  4. Evaluate project work to ensure effectiveness, technical adequacy, or compatibility in the resolution of complex electronics engineering problems.

  5. Analyze electronics system requirements, capacity, and cost, to determine project feasibility.

  6. Operate computer-assisted engineering and design software to perform electronics engineering tasks.

  7. Implement scalable test benches including checkers, reference models, and coverage groups in System Verilog.

  8. Keep track of coverage metrics and bugs that are encountered and fixed.

  9. Implement self-testing directed and random tests.

  10. Support post silicon bring-up and debug activities.

Minimum Qualifications:

Minimum Qualifications:

  1. Requires Bachelor's degree in Computer Science, Electrical Engineering, Electronics, or related field and 60 months experience in the job offered or in a computer-related occupation. Requires 24 months of experience involving the following:

    1. Testbench Architecture
    1. Universal Verification Methodology (UVM)
    1. Verilog, System Verilog, and System Verilog Assertions (SVA)
    1. Functional Coverage and code coverage
    1. UVM RAL (Register Access Layer) integration
    1. Constraint Random verification environment
    1. AMBA-AHB and AXI bus protocols
    1. Waveform viewing tools, including VCS, DVE, and Verdi.

Public Compensation:

$222,114/year to $234,520/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

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